Xilinx ISE Design Suite v13.4 英文正式版(電子設計套件軟體)(DVD9版)
Check instructions in /crack directory.
Xilinx ISE Design Suite 設計套件是面向 Virtex -6 和 Spartan -6 FPGA 系列並針
對生
產力精心優化的工具套件，在降低功耗與成本方面取得了突破性進展。作為業界唯一一
款特
定領域的設計套件，賽靈思最新版本的發佈， 是這一行業屢獲殊榮的軟體不斷發展和演
進的
又一重要一步，它將進一步提高設計生產力和系統性能，使邏輯、嵌入式、數字信號處
理
(DSP) 和系統設計人員能夠更輕鬆地推出更複雜的創新型可編程電子產品，從而加速產
品上
市進程並提升產品質量。
ISE DESIGN SUITE 的主要優勢
針對 VIRTEX -6 和 SPARTAN -6 FPGA：
● 利用自動時鐘門控技術將動態功耗降低30%之多
● 利用第四代部分重配置設計流程降低系統成本
● PlanAhead - 面向邏輯設計人員的新款 RTL 到比特流設計流程
● 利用 AXI4 介面實現即插即用式 FPGA 設計
全新發佈的ISE Design Suite 13.3設計套件，其中結合了許多全新功能，能讓數字信號
處理器
（DSP）設計業者針對無線、醫療、航太與國防、高效能運算與視訊應用等設計，輕鬆地
加入位
精準的完全客制化單、雙精度浮點運算功能。客戶可透過System Generator for DSP，
以及運用
Xilinx Floating-Point Operator IP LogiCORE執行上述設計流程。結合單、雙精度、
以及具備
完全客制化精度浮點運算功能，加上System Generator for DSP帶來的高生產力，DSP設
計業者可
在這種環境中輕鬆地設計、模擬和建置各種浮點運算設計，並能對矽元件部分及系統所
需要的功
耗擁有更佳的掌握度。
賽靈思的Floating-Point Operator核心可讓各種浮點計算作業能在FPGA中執行。當透過
CORE
Generator工具產生核心時，該作業即可確定，而現在則由System Generator來執行這項
工作，同
時每項作業變數有一個共享的AXI-4串流介面。以往客戶可運用CORE Generator中的完全
客制化精
度浮點運算IP，在單賽靈思FPGA元件中加入浮點運算設計。然而，要採用這種設計流程
，業者必須
瞭解VHDL或Verilog語言，而且對DSP研發業者來說仿真作業亦是一大挑戰。但有了ISE
Design Suite
13.3設計套件後，研發業者現在可透過運用The Math Works』 Simulink的各種仿真功能
，從更高的
抽像層瞭解他們的系統，可確保設計對精確度的要求。
ISE Design Suite 13.3設計套件也加入了Red Hat Enterprise Linux 6作業系統，並針
對邏輯、嵌
入式和系統版本用戶提供加強的生產力功能。所有版本都內含即插即用IP的加強功能和
支援7系列
FPGA。嵌入式與系統版本內含Platform Studio簡單易用的強化功能，其中包括全新的圖
形化設計視
圖（Graphical Design View）功能。邏輯版內含支援PlanAhead設計分析工具的生產力
強化功能，包
括針對HDL檔案的圖形階層查看器（Graphical Hierarchy Viewer）。
The ISE Design Suite: System Edition
provides a comprehensive suite of
integrated development environment,
software tools, configuration wizards,
and IP that facilitates your design
and utilizes all of the flexibility
offered by a programmable platform.
Xilinx CORE Generator?System,
included in all Editions of the ISE
Design Suite, accelerates design time
by providing access to highly
parameterized Intellectual Properties
(IP) for Xilinx FPGAs and is included
in the ISE Design Suite. The available
user-customizable IP functions range
in complexity from commonly used
functions, such as memories and FIFOs,
to system-level building blocks, such
as filters and transforms. Using these
IP blocks can save days to months of
design time. The highly optimized IP
allows FPGA designers to focus efforts
on building designs quicker while
helping bring products to market
faster.
Xilinx introduced the ISE Design Suite software to enable
breakthrough optimizations for power and cost with greater design
productivity. For the first time, ISE design tools deliver 'intelligent'
clock-gating technology that reduces dynamic power consumption by as
much as 30 percent. The new suite also provides advances in
timing-driven design preservation, AMBA 4 AXI4-complaint IP support for
plug-and-play design, and an intuitive design flow with
fourth-generation partial reconfiguration capabilities that lowers
system cost for a broad range of high performance applications.
With full production support for all Xilinx Virtex-6 and Spartan-6
FPGA families, the ISE release continues its evolution as the
industry's only domain-specific design suite with interoperable design
flows and tool configurations for logic, digital signal processing
(DSP), embedded processing, and system-level design. In addition, Xilinx
incorporated a number of software infrastructure and methodology
enhancements that improve run time, streamline system integration, and
expand IP interoperability across its latest generation device families
and Targeted Design Platforms.
Intelligent Automation for Power Optimization
ISE Design Suite introduces the FPGA industry's first intelligent
clock-gating technology with fully automated analysis and fine-grain
(logic slice) optimization capabilities specifically developed to reduce
the number of transitions, a primary contributing factor of dynamic
power dissipation in digital designs. The technology works by analyzing
designs using a series of unique algorithms to detect sequential
elements...
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